1. Field of the Invention
This invention relates to a process for the filling, with copper, of trench and via openings in a dielectric layer of an integrated circuit structure in a manner which will remove impurities and promote the growth of larger copper grain sizes to thereby lower the resistivity and stress, and enhance electromigration (EM) of the copper metal filler.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO2) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon the resistivity of the deposited copper is lowered, Technologies of Newport, Gwent, U.K.
The process is said to react methyl silane (CH3—SiH3) with hydrogen peroxide (H2O2) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400° C. to remove moisture.
An article by S. McClatchie et al. entitled “Low Dielectric Constant Oxide Films Deposited Using CVD Techniques”, published in the 1998 Proceedings of the Fourth International Dielectrics For ULSI Multilevel Interconnection Conference (Dumic) held on Feb. 16-17, 1998 at Santa Clara, Calif., at pages 311-318, also describes the formation of methyl-doped silicon oxide by the low-k Flowfill process of reacting methyl silane with H2O2 to achieve a dielectric constant of ˜2.9.
The above-mentioned shrinking of integrated circuits and the concurrent ever increasing demands for faster speeds, has also resulted in renewed interest in the use of copper as a filler material for vias and contact openings instead of tungsten, as well as for use in metal lines or interconnects instead of aluminum because of the well known low electrical resistance of copper, compared to either aluminum or tungsten.
However, it has been found that at the dimensions utilized in forming wiring structures using copper in integrated circuit structures, problems arise when attempting to conventionally pattern a layer of copper through a mask in the manner in which aluminum and tungsten wiring structures are formed.
This, in turn, has led to the formation of copper-filled vias and copper metal lines by a different type of construction known as a damascene (when only metal lines or copper-filled vias are to be formed), or a dual damascene construction (when copper metal-filling of vias and metal lines (formed in a second dielectric layer above the via-containing layer), is performed in the same step). In, for example, a single damascene construction, a first or second layer of dielectric material (preferably a low k dielectric material) is initially formed over an integrated circuit structure, and the desired pattern of vias or trenches is etched in the dielectric layer as a series of vertical openings. The filler metal such as copper (as well as other layers of conductive material, such as barrier and adhesion-promoting materials) are then deposited in each type of openings and over the top surface of the dielectric layer. Planarization processes such as a chemical/mechanical polishing (CMP) process are then applied to the upper surfaces of the structure to remove all excess conductive filler material from the upper surface of the dielectric material, leaving a series or pattern of copper-filled vias or trenches. The copper-filled and planarized integrated circuit structure is then subject to anneal. Such a construction is illustrated in the flow sheet of prior art FIG. 1.
In the dual damascene process, a thicker dielectric layer for both vias and trenches is formed over the integrated circuit structure. Subsequently, depending on the integration scheme, the layer is processed to either form the vias first and then form the trenches or, vice versa, the trenches are formed first followed by formation of the vias. Once the vias and trenches are formed, copper filler material is then deposited into both types of features in the same step, once again followed by planarizing back to the dielectric layer using a CMP process.
However, even when the damascene processes are successfully implemented, and filled copper metal lines and vias have been formed, the formation of a high resistivity copper filler material in the trenches and vias may occur. According to Charles Kittel, in Introduction to Solid State Physics, p. 145 (1986), the electrical resistivity of metals consists of two sources of scattering or collisions by the conduction electrons: (1) lattice phonons and (2) impurities and\or imperfections.
Typically, at room temperature, the lattice phonon component dominates, while at liquid Helium temperatures, the impurity/imperfection component does. However, in copper interconnects, the contribution to high resistivity from impurity collisions cannot be neglected and has been estimated by S. M Rossnagel, [IITC 2(2001)], to become increasingly dominant when the gap dimension reaches 0.1 micrometer (μm) and below.
The elements that contribute to the “impurity” component can be characterized as (1) impurity atoms and molecules (carbon, sulfur, chlorine, etc. incorporated into the copper filler material during the deposition (electroplating) process); (2) lattice imperfections at grain boundaries; and (3) lattice imperfections at the grain-sidewall interfaces. Reduction of these sources will result in improved metal line resistivity.
With respect to the lattice imperfections at grain boundaries and grain-sidewall interfaces, impurities in the copper apparently lead to smaller grain size which, in turn, leads to higher resistivities of the deposited copper. The smaller size grains in the metal lines and contacts (vias), implies that the impurity levels are highest in these metal lines and vias since the impurities are suspected to be the chief hindrance to grain coalescence. These impurities will directly or indirectly contribute to the increase overall resistivity as well. Such increases in resistivity, in turn, can limit the usefulness of copper as a filler material as it counters copper's lower bulk resistivity.
Another impact of the smaller size grains in metal lines and vias (resulting in an increase in grain boundary density and impurity levels) is the potential decrease in electro-migration (EM) performance.
A further impact of the smaller and inconsistent grain structures (and sizes) results from the “non-optimal” stress distribution within the metal structures. The stress relaxation process during subsequent processing can result in stress-induced voids, and, therefore, device failures. The grain structures and sizes can also impact the post-planarization (e.g., CMP) deflectivity, which has been linked to reduced EM performance.
Various published experimental data show close relationship between the grain growth and impurity levels. T. Ritzdorf et al. [IITC 287 (1999)] observes slower transformation (self annealing or grain growth/coalescence) with higher level of impurity in electroplating bath, while S. Brongersma et al. [IITC 290 (1999)] reports desorption of volatile chemicals with grain growth transformation (using TOF-SIMS).
Some of the suggestions for this transformation mechanism (in electroplated Cu) are as follows. S. Brongersma et al., suggests that the additives (in electroplating solution and incorporated in Cu film) segregate to grain boundaries and inhibit grain growth, if not removed or desorbed. He also suggests that the untransformed matrix has a dense grain boundary network (therefore, small grains), which provides the diffusion path for impurities and high driving force for grain growth.
In a University of California-Berkeley extension course entitled “Copper Interconnect Technology” (April, 2002), S. P. Hau-Riege described, on pages 129-137, the effect of impurity diffusion on phase transformation with the Johnson-Mehl-Avrami-Kolmogoroff Theory [a phenomenological model for 11 order phase transformation through nucleation and growth], as analogously applied by Ramanan et al. [J. Appl. Phys. 53, 2273 (1982)], and found agreement with Brongersma. The activation energy, for grain growth, was equated with the impurity diffusing through the untransformed matrix.
The grain growth, in copper film, is activated by “impurity-free” interfacial (grain boundary) strain energy and is hampered by impurities, which need grain boundary networks to diffuse. The consequences of grains in trenches and vias is as follows: unless there are “percolating” grain boundary paths, the impurities with trenches and vias will be trapped and remain a hindrance to grain growth, resulting in the high resistivity, lowered EM performance, and non-optimal stress distribution discussed above.
Interfacial strain between two dissimilar non-reacting materials typically results from the differences in lattice structure, lattice parameters, and coefficient of thermal expansion (CTE). The stress-induced voiding will occur when this stress is at a certain critical level (above the activation energy for void nucleation and growth) when the kinetic hindrance is absent. The level of stress would be particularly significant within the metal lines and vias, wherein there are several sources of stress: grain-to-grain growth, grain-to-sidewall, grain-to-subsequent layer, and impurities.
S. Brongersma, et al., [IITC 290 (1999)] reports that the stress was being relieved as the grain growth/coalescence transformation occurred. Therefore, if the impurity levels (the inhibitor to grain growth, within the metal lines and trenches) can be reduced, the grain growth will be promoted to reduce the stress, and thereby reduce the stress-induced voiding during subsequent processing.
Thus the impurity level ties into some key factors that determine the properties of the copper back end of the line (BEOL) performance, including stress distribution, resistivity and post-CMP deflectivity, the electromigration (EM), and the average grain size of the copper metal deposited in the trenches and vias.